1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device having a virtual-ground memory array.
2. Description of the Related Art
In the virtual-ground memory array of flash memories, bit lines are formed as diffusion layers, and a source and a drain will switch positions depending on how the diffusion layers of two bit lines are coupled to the ground potential and the power supply potential.
FIG. 1 is a circuit diagram showing a portion of a virtual-ground memory array.
The virtual-ground memory array of FIG. 1 includes memory cells 10-1 through 10-7, selection transistors 11-1 through 11-8, sub-bit lines BL1 through BL8, and selection lines SL0 through SL3. When the memory cell 10-2 is to be selected, a word line WL is activated to select all the memory cells connected to the word line WL, and the selection lines SL1 and SL3 are activated to make the selection transistors 11-2 and 11-3 conductive. With this setting, one of the sub-bit lines BL2 and BL3 is coupled to HIGH to serve as a drain, and the other one is coupled to LOW to serve as a source, thereby reading data from the memory cell 10-2.
When data of a selected memory cell is to be retrieved as described above, a leak current runs from the sub-bit line BL3 to an unselected memory cell 10-3 if the sub-bit line BL3 is the one that is set at the HIGH potential. This undesirably prevents the potential of the selected memory cell from rising to a sufficient level in a short time, resulting in a decrease of a sense margin, which further results in a degradation of data retrieval efficiency.
Accordingly, there is a need for a semiconductor memory device which is provided with a mechanism to prevent a leak current in a virtual-ground memory array.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a nonvolatile semiconductor memory device according to the present invention includes a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells, first and second selection lines, first and second selection transistors which become conductive in response to activation of the first selection line, a third selection transistor which become conductive in response to activation of the second selection line, a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor, a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor, and a third main bit line which is coupled to a sub-bit line adjacent to the sub-bit line situated on the drain side of the selected memory cell through another one of the second selection transistor and the third selection transistor, and is coupled to a potential substantially the same as the drain potential.
In the nonvolatile semiconductor memory device as described above, when data of a selected memory cell is to be read, the first main bit line supplies the drain potential through the first selection transistor, and the second main bit line supplies the source potential through one of the second selection transistor and the third selection transistor, with the third main bit line supplying the potential substantially the same as the drain potential to a sub-bit line adjacent to the sub-bit line serving as the drain through the other one of the second selection transistor and the third selection transistor. As a result, the sub-bit line of an unselected memory cell is set to the same potential as the sub-bit line serving as the drain, thereby preventing a leak current from leaking from the sub-bit line of the drain to the sub-bit line of the unselected memory cell.
In the configuration described above, the potentials of the first through third main bit lines can be supplied by activating only two selection lines, so that the invention is implemented without increasing the numbers of selection lines and selection transistors compared with the related-art configuration.